1. Field of the Invention
The invention relates to a semiconductor device, and in particular relates to an HVMOS and a method for fabricating thereof
2. Description of the Related Art
High-voltage metal-oxide-semiconductors (HVMOS) are MOS devices for use with high voltages, which may be, but not limited to, voltages higher than the voltage supplied to the I/O circuit. HVMOS devices may function as switches and are broadly utilized in audio output drivers, CPU power supplies, power management systems, AC/DC systems, LCD or plasma television drivers, automobile electronic components, PC peripheral devices, small DC motor controllers, and other consumer electronic devices.
FIG. 1 shows a cross-sectional view of a conventional high-voltage NMOS transistor structure. The high-voltage NMOS (HVNMOS) transistor structure 101 includes a gate 105 overlying an area of a P-type substrate 100, a deep N-well 110 formed in the P-type substrate 100, an N-well 120 formed in the substrate 100 proximate to a first sidewall 105a of the gate 105, and a P-well 130 formed in the P-type substrate 100 proximate to a second sidewall 105b of the gate 105 opposite to the first sidewall 105a, wherein a P-N junction 140 is formed at the interface between the N-well 120 and the P-well 130. The P-well 130 has an overlapping area with the gate 104 which is larger than that of the N-well 120. An N+ drain region 150 is in the N-well 120 and aligned to the first sidewall 105a of the gate 104. An N-type source region 155 includes an N+ region 155a and an N-type lightly doped region 155b formed in the P-well 130.
The above-described HVNMOS transistor structure 100 can tolerate high voltages introduced from the N+ drain region. However, since the size of IC devices continue to shrink via new generation technologies, the above-described HVNMOS transistor structure 100 is not suitable for advanced ICs having a reduced gap between the P-N junction and the N+ drain region. A highly dosed N-type dopant in the N+ drain region is prone to diffuse the P-N junction 140 and the gate 104 due to the reduced gap between the P-N junction 140 and the N+ drain region 150, which results in a more serious hot carrier injection (HCI) effect and degraded time-dependent dielectric breakdown (TDDB).